FPGA Physical Design

The physical design of Field Programmable Gate Array (FPGA) fabric is a strenuous and labor-intensive task, primarily due to t he use of full custom design methodology to achieve aggressive Power, Performance, and Area (PPA) metric. The custom design approach results in poor process portability and a longer development cycle, making it incompatible with the modern FPGA requirements. On the other hand, using a fully automated ASIC design methodology provides a much shorter development cycle but results in poor scalability and performance degradation. A dedicated and well-optimized semi-custom design approach is essential to minimize the performance gap without significantly increasing development time.

Our work aims to provide a framework Physical Design and Floorplanning for a Tileable FPGA Architectures (OpenFPGA-Physical), and to provide a semi-custom design methodology to minimize the gap between fully custom and fully automated FPGA design methodologies. Besides physical design, we also want to explore t he FPGA architecture for combinational cyclic circuit implementation.

This research effort is funded by RapidSilicon