PI Publication List (as of December 2022)

Articles Published in Refereed Publications (Journals)

  1. W. Lau Neto, Y. Li, P.-E. Gaillardon, C. Yu, "End-to-end Automatic Logic Optimization Exploration via Domain-specific Multi-armed Bandit", Transactions on Computer-Aided Design of Integrated Circuits and System", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022.

  2. A. Alacchi, P. -E. Gaillardon, "Programmable Local Clock SET Filtering for SEE-Resistant FPGA," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 9, pp. 3879-3883, Sept. 2022, doi: 10.1109/TCSII.2022.3172390

  3. G. Ammes, W. Lau Neto, P. Butzen, P.-E. Gaillardon, R. Ribas, "A Two-Level Approximate Logic Synthesis Combining Cube Insertion and Removal", Transactions on Computer-Aided Design of Integrated Circuits and System, vol. 41, no. 1, pp. C3-C3, January 2022.

  4. E. Giacomin, S. Gudaparthi, J. Boemmels, R. Balasubramonian, F. Catthoor, P.-E. Gaillardon, "A Multiply-And-Accumulate Array for Machine Learning Applications Based on a 3D Nanofabric Flow", IEEE Transactions on Nanotechnologies, vol.20, pp. 873-882, December 2021.

  5. P. Cadareanu, P.-E. Gaillardon, "A TCAD Simulation Study of Three-Independent-Gate Field-Effect Transistors at the 10-nm Node," IEEE Transactions on Electron Devices, vol. 68, no. 8, pp. 4129-4135, August 2021.

  6. P. Cadareanu, J. Romero-Gonzalez, P.E. Gaillardon, "Parasitic Capacitance Analysis of Three-Independent-Gate Field-Effect Transistors", IEEE Journal of the Electron Devices Society, pp. 1-9, April 2021.

  7. S. Reda, L. Stok, P.-E. Gaillardon, "Guest Editors’ Introduction: The Resurgence of Open-Source EDA Technology", IEEE Design &Test, vol. 38(2), April 2021

  8. A. Eliahu, R. Ronen, P.-E. Gaillardon, S. Kvatinsky, "multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-low-power Architectures", IEEE Journal on Emerging Technologies in Computing Systems, vol. 17, no. 24, pp. 1-27, April 2021.

  9. K. Kelly, W. Xing, T. Sayahi, L. Mitchell, T. Becnel, P.-E. Gaillardon, M. Meyer, R. Whitaker, "Community-Based Measurements Reveal Unseen Differences during Air Pollution Episode," Environmental Science & Technology, vol. 55, no. 1, January 2021.

  10. E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, P.-E. Gaillardon, G. De Micheli, "Extending Boolean Methods for Scalable Logic Synthesis," IEEE Access, vol. 8, pp. 226828-226844, December 2020.

  11. T. Sayahi, A. Garff, T. Quah, K. Le, T. Becnel, K. Powell, P.-E. Gaillardon, A. Butterfield, K. Kelly, "Long-term Calibration Models to Estimate Ozone Concentrations with a Metal Oxide Sensor," Environmental Pollution, vol. 267, 115363, December 2020.

  12. D. Mallia, A. Kochanski, K. Kelly, R. Whitaker, W. Xing, L. Mitchell, A. Jacques, A. Farguell, J. Mandel, P.-E. Gaillardon, T. Becnel, S. Krueger, "Evaluating Wildfire Smoke Transport Within a Coupled Fire‐Atmosphere Model Using a High‐Density Observation Network for an Episodic Smoke Event Along Utah's Wasatch Front," Journal of Geophysical Research: Atmospheres, vol. 125, no. 20, October 2020.

  13. X. Tang, E. Giacomin, A. Alacchi, B. Chauviere, P.-E. Gaillardon, "OpenFPGA: An Opensource Framework for Agile Prototyping Customizable FPGAs", IEEE Micro, vol. 40, no. 4 , pp. 41-48, July/August 2020.

  14. C. Mullen, T. W. Collins, W. Xing, R. Whitaker, T. Sayahi, T. Becnel, P. Goffin, P.-E. Gaillardon, M. Meyer, K. E Kelly, "Patterns of distributive environmental inequity under different PM2.5 air pollution scenarios for Salt Lake County public schools", Environmental Research, Volume 186, July 2020, 109543.

  15. W. Lau Neto, V. Possani, F. Marranghello, J. Matos, P.-E. Gaillardon, A. Reis, R.P. Ribas, "Exact Benchmark Circuits for Logic Synthesis," IEEE Design & Test, vol. 37, no. 3 , pp. 51-58, June 2020.

  16. D. Vana, P.-E. Gaillardon, A. Teman, "C2TIG: Dynamic C2MOS Design Based on Three-Independent-Gate Field-Effect Transistors," IEEE Transactions on Nanotechnology, vol. 19, no. 1, pp. 123-136, January 2020.

  17. T. Becnel, K. Tingey, J. Whitaker, T. Sayahi, K. Le, P. Goffin, A. Butterfield, K. Kelly, P.-E. Gaillardon, "A Distributed Low-Cost Pollution Monitoring Platform," IEEE Internet of Things Journal, vol. 6, no. 6 , pp. 10738-10748, December 2019.

  18. T. Sayahi, D. Kaufman, T. Becnel, K. Kaur, A. Butterfield, S. Collingwood, Y. Zhang, P.-E. Gaillardon, K. Kelly, "Development of a calibration chamber to evaluate the performance of low-cost particulate matter sensors," Environmental Pollution, vol. 255, pp. 932-940, December 2019.

  19. G. Resta, A. Leonhardt, Y. Balaji, S. de Gendt, P.-E. Gaillardon, G. De Micheli, "Devices and Circuits using Novel 2-Dimensional Materials: a Perspective for Future VLSI Systems," IEEE Transactions on Very Large Scale Integration Systems. Regular Papers. vol. 27, no. 7 , pp. 1486-1503, July 2019.

  20. X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, "FPGA-SPICE: A Simulation-based Architecture Evaluation Framework for FPGAs," IEEE Transactions on Very Large Scale Integration Systems. Regular Papers. vol. 27, no. 3, pp. 637-650, March 2019. RANKED within the IEEE TVLSI TOP 10 POPULAR ARTICLES from February to August 2019.

  21. E. Giacomin, T. Greenberg-Toledo, S. Kvatinsky, P.-E. Gaillardon, "A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications," IEEE Transactions on Circuits and Systems I: Regular Papers. vol. 66, no. 2, pp. 643-654, February 2019.

  22. A. Levisse, P.-E. Gaillardon, B. Giraud, I. O'Connor, J. P. Noel, M. Moreau, J. M. Portal, "Resistive Switching Memory Architecture Based on Polarity Controllable Selectors," IEEE Transactions on Nanotechnology, vol. 18, pp. 183-194, December 2018.

  23. E. Giacomin, P.-E. Gaillardon, "A Resistive Random Access Memory Addon for the NCSU FreePDK 45nm," IEEE Transactions on Nanotechnology, vol. 18, no. 1, pp. 68-72, November 2018.

  24. X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, "Post-P&R Performance and Power Analysis for RRAM-based FPGAs," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 8, no. 3, pp. 639-650, September 2018.

  25. S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, "Logic Synthesis for RRAM-based In-Memory Computing," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 37, no. 7, pp. 1422-1435, July 2018.

  26. G. Resta, Y. Balaji, D. Lin, I. P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, "Doping-Free Complementary Logic Gates Enabled by Two-Dimensional Polarity-Controllable Transistors (supporting information)," ACS Nano, vol. 12, no. 7, pp. 7039–7047, June 2018.

  27. J. Romero-Gonzalez, P.-E. Gaillardon, "BCB Evaluation of High-Performance and Low-Leakage Three-Independent-Gate Field Effect Transistors," IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, vol. 4, no. 1, pp. 1-9, June 2018.

  28. K. Le, A. Butterfield, K. Kelly, P.-E. Gaillardon, K. Tingey, T. Becnel, "Building Air Quality Sensors and Inspiring Citizen Scientists," Chemical Engineering Education, vol. 52, no. 3, pp. 193-201, June 2018. William H. Corcoran Award for the best paper in Chemical Engineering Education.

  29. T-H. Lin, T. Margossian, L-Q. Zheng, S. Kumar, I. Morozau, O. Sereda, D. Zemlyanov, C-J. Shih, R. Zenobi, D. Baudouin, G. De Micheli, P-E. Gaillardon, C. Copéret, "Conformal Deposition of Conductive Single-Crystalline Cobalt Silicide Layer on Si Wafer via a Molecular Approach," Chemistry of Materials, vol. 30, no. 6, pp. 2168-2173, February 2018.

  30. A. Biscontini, M. Thammasack, G. De Micheli, P.-E. Gaillardon,"An FPGA-Based Test System for RRAM Technology Characterization," IEEE Transactions on Nanotechnology, vol. 17, no. 1, pp. 177-183, January 2018.

  31. M. Thammasack, G. De Micheli, P.-E. Gaillardon, "Effect of O2- migration in Pt/HfO2/Ti/Pt structure," Journal of Electroceramics, vol. 39, no. 1-4, pp. 137-142, December 2017.

  32. M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, "Exact Synthesis of Majority-Inverter Graphs and Its Applications," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 36, no. 11, pp. 1842-1855, November 2017.

  33. M. Soeken, P.-E. Gaillardon, S. Shirinzadeh, R. Drechsler, G. De Micheli, "A PLiM Computer for the IoT," Computer Magazine, vol. 50, no. 6, pp. 35-40, June 2017.

  34. X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, "Circuit Designs of High-performance and Low-power RRAM-based Multiplexers based on 4T(ransistor)1R(RAM) Programming Structure," IEEE Transactions on Circuits and Systems - I, vol. 64, no. 5, pp. 1173-1186, May 2017. RANKED within the IEEE TCAS-I TOP POPULAR ARTICLES in May 2017.

  35. X. Tang, G. De Micheli, P.-E. Gaillardon, "A High-performance FPGA Architecture Using One-Level RRAM-based Multiplexers," IEEE Transactions on Emerging Topics in Computing (TETC), vol. 5, no. 2, pp. 210-222, April-June 2017.

  36. G. Resta, T. Agarwal, D. Lin, I. P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, "Scaling trends and performance evaluation of 2-dimensional polarity-controllable FETs," Scientific Reports, 7:45556, March 2017.

  37. D.-Y. Jeon, J. Zhang, J. Trommer, S. J. Park, P.-E. Gaillardon, G. De Micheli, T. Mikolajick, W. M. Weber, "Operation regimes and electrical transport of steep slope Schottky Si-FinFETs," Journal of Applied Physics, vol. 121, no. 6, pp. 064504-1-064504-7, February 2017.

  38. T.-H. Lin, T. Margossian, M. De Marchi, M. Thammasack, D. Zemlyanov, S. Kumar, J. Jagielski, L.-Q. Zheng, C.-J Shih, R. Zenobi, G. De Micheli, D. Baudouin, P.-E. Gaillardon, C. Copéret, "Low Temperature Wet Conformal Nickel Silicide Deposition for Transistor Technology through an Organometallic Approach," ACS Applied Materials & Interfaces, vol. 8, no. 5, pp. 4948-4955, January 2017.

  39. M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, "A Continuous Compact DC Model for Dual-Independent-Gate FinFETs," IEEE Journal of the Electron Devices Society, vol. 5, no. 1, pp. 23-31, January 2017.

  40. J. Tranchant, J. Sandrini, E. Janod, D. Sacchetto, B. Corraze, M.-P. Besland, J. Ghanbaja, G. De Micheli, P.-E. Gaillardon, L. Cario, "Control of Resistive Switching in Mott Memories Based on TiN/AM4Q8/TiN MIM Devices," ECS Transactions, vol. 75, no. 31, pp. 3-12, January 2017.

  41. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation," Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 12, pp. 1995-2007, December 2016.

  42. H. Ghasemzadeh, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez, M. Sonza Reorda, "A Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors," ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 2, pp. 16:1-16:13, November 2016.

  43. L. Amarú, P.-E. Gaillardon, A. Chattopadhyay, G. De Micheli, "A Sound and Complete Axiomatization of Majority-n Logic," IEEE Transactions on Computers, vol. 65, no. 9, pp. 2889-2895, September 2016.

  44. G. Resta, S. Sutar, Y. Balaji, D. Lin, P. Raghavan, I. Radu, F. Catthoor, A. Thean, P.-E. Gaillardon, G. De Micheli, "Polarity control in WSe2 double-gate transistors," Scientific Reports, 6:29448, July 2016.

  45. Y. Bi, K. Shamsi, J.-S. Yuan, P.-E. Gaillardon, G. De Micheli, X. Yin, X. S. Hu, M. Niemier, Y. Jin, "Emerging Technology based Design of Primitives for Hardware Security," ACM Journal on Emerging Technologies in Computing Systems, vol. 13, no. 1, pp. 3:1-3:19, June 2016.

  46. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Majority-Inverter Graph: A New Paradigm for Logic Optimization," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, no. 5, pp. 806-819, May 2016. RANKED within the IEEE TCAD TOP-10 POPULAR ARTICLES in May, June, July, August and September 2016. 2018 IEEE CEDA Pederson Award

  47. X. Tang, G. Kim, P.-E. Gaillardon, G. De Micheli, "A Study on the Programming Structures for RRAM-based FPGA Architectures," IEEE Transactions on Circuits and Systems - I, vol. 63, no. 4, pp. 503-516, April 2016. RANKED within the IEEE TCAS-I TOP POPULAR ARTICLES in April and May 2016

  48. J. Sandrini, M. Barlas, M. Thammasack, T. Demirci, M. De Marchi, D. Sacchetto, P.-E. Gaillardon, G. De Micheli, Y. Leblebici, "Co-design of ReRAM Passive Crossbar Arrays Integrated in 180nm CMOS Technology," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 6, no. 3, pp. 339-351, April 2016.

  49. A. Antidormi, S. Frache, M. Graziano, P.-E. Gaillardon, G. Piccinini, G. De Micheli, "Computationally Efficient Multiple-Independent-Gate Device Model," IEEE Transactions on Nanotechnology, vol. 15, no. 1, pp. 2-14, January 2016.

  50. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires," IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117-1126, November 2015.

  51. J. Zhang, J. Trommer, W. Weber, P.-E. Gaillardon, G. De Micheli, "On Temperature Dependency of Steep Subthreshold Slope in Dual-Independent-Gate FinFET," IEEE Journal of the Electron Devices Society, vol. 3, no. 6, pp. 452-456, November 2015.

  52. L. Amarú, P.-E. Gaillardon, S. Mitra, G. De Micheli, "New Logic Synthesis As Nanotechnology Enabler," Proceedings of the IEEE, vol. 103, no. 11, pp. 2168-2195, October 2015.

  53. P.-E. Gaillardon, X. Tang, G. Kim, G. De Micheli, "A Novel FPGA Architecture based on Ultra-Fine Grain Reconfigurable Logic Cells," IEEE Transactions on Very Large Scale Integration Systems, vol. 23, no. 10, pp. 2187-2197, October 2015.

  54. P.-E. Gaillardon, E. Beigné, S. Lesecq, G. De Micheli, "A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems," ACM Journal on Emerging Technologies in Computing Systems, vol. 12, no. 2, pp. 12:1-12:26, August 2015.

  55. J. Sandrini, M. Thammasack, T. Demirci, P.-E. Gaillardon, D. Sacchetto, G. De Micheli, Y. Leblebici, "Heterogeneous Integration of ReRAM Crossbars in 180nm CMOS BEoL Process," Microelectronic Engineering, vol. 145, pp. 62-65, September 2015.

  56. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 4, no. 4, pp. 487-500, December 2014. RANKED within the IEEE JETCAS TOP-10 POPULAR ARTICLES in January and February 2015

  57. J. Zhang, M. De Marchi, D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Polarity-Controllable Silicon Nanowire Transistors with Dual Threshold Voltages," IEEE Transactions on Electron Devices, vol. 61, no. 11, pp. 3654-3660, November 2014.

  58. M. De Marchi, D. Sacchetto, J. Zhang, S. Frache, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Top-Down Fabrication of Gate-All-Around Vertically-Stacked Silicon Nanowire FETs with Controllable Polarity," IEEE Transactions on Nanotechnology, vol. 13, no. 6, pp. 1029-1038, November 2014.

  59. L. Amarú, P.-E. Gaillardon, G. De Micheli, "A Circuit Synthesis Flow for Controllable-Polarity Transistors," IEEE Transactions on Nanotechnology, vol. 13, no. 6, pp. 1074-1083, November 2014.

  60. I. Kazi, P. Meinerzhagen, P.-E. Gaillardon, D. Sacchetto, Y. Leblebici, A. Burg, G. De Micheli, "Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design," IEEE Transactions on Circuits and Systems - I, vol. 61, no. 11, pp. 3155-3164, November 2014.

  61. J. Zhang, X. Tang, P.-E. Gaillardon, G. De Micheli, "Configurable Circuits Featuring Dual-Threshold-Voltage Design with Three-Independent-Gate Silicon Nanowire FETs," IEEE Transactions on Circuits and Systems - I, vol. 61, no. 10, pp. 2851-2861, October 2014.

  62. M. De Marchi, J. Zhang, S. Frache, D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Configurable Logic Gates Using Polarity Controlled Silicon Nanowire Gate-All-Around FETs," IEEE Electron Device Letters, vol. 35, no. 8, pp. 880-882, August 2014.

  63. S. Bobba, J. Zhang, P.-E. Gaillardon, H.-S. P. Wong, S. Mitra, G. De Micheli, "System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits," ACM Journal on Emerging Technologies in Computing Systems, vol. 10, no. 4, May 2014.

  64. P.-E. Gaillardon, L. Amarú, S. Bobba, M. De Marchi, D. Sacchetto, G. De Micheli, "NanoWire Systems: Technology and Design," Invited Paper, Philosophical Transactions of the Royal Society of London A, vol. 372, no. 2012, March 2014.

  65. L. Amarú, P.-E. Gaillardon, J. Zhang, G. De Micheli, "Power-Gated Differential Logic Style Based on Double-Gate Controllable Polarity Transistors," IEEE Transactions on Circuits and Systems - II, vol. 60, no. 10, pp. 672-676, October 2013.

  66. D. Sacchetto, P.-E. Gaillardon, M. Zervas, S. Carrara, G. De Micheli, Y. Leblebici, "Applications of Multi-Terminal Memristive Devices: A Review," IEEE CAS Magazine, vol. 13, no. 2, pp. 23-41, May 2013.

  67. P.-E. Gaillardon, D. Sacchetto, G. Betti Beneventi, M. H. Ben Jamaa, L. Perniola, F. Clermidy, I. O'Connor, G. De Micheli, "Design and Architectural Assessment of 3-D Resistive Memory Technologies in FPGAs," IEEE Transactions on Nanotechnology, vol. 12, no. 1, pp. 40-50, January 2013.

  68. P. Batude, T. Ernst, J. Arcamone, G. Arndt, P. Coudrain, P.-E. Gaillardon, "3D sequential integration: a key enabling technology for heterogeneous co-integration of new function with CMOS," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 2, no. 4, pp. 714-722, December 2012.

  69. M. H. Ben Jamaa, P.-E. Gaillardon, F. Clermidy, I. O'Connor, D. Sacchetto, G. De Micheli, Y. Leblebici, "Silicon Nanowire Arrays and Crossbars: Top-Down Fabrication Techniques and Circuit Applications," Science of Advanced Materials, vol.3, no.3, pp.466-476, June 2011.

  70. M. H. Ben Jamaa, P.-E. Gaillardon, S. Frégonèse, M. De Marchi, G. De Micheli, T. Zimmer, I. O'Connor and F. Clermidy, "FPGA Design with Double-Gate Carbon Nanotube Transistors," The Electro-Chemical Society Transactions, vol. 34, no. 1, pp. 1005-1010, 2011.

  71. P.-E. Gaillardon, I. O'Connor, M. Amadou, J. Liu, F. Clermidy, G. Nicolescu, "Matrix Nanodevice-Based Logic Architectures and Associated Functional Mapping Method," ACM Journal on Emerging Technologies in Computing Systems, vol. 7, no. 1, pp. 3:1-3:23, January 2011.

  72. I. O'Connor, J. Liu, D. Navarro, R. Daviot, N. Abouchi, P.-E. Gaillardon, F. Clermidy, "Molecular electronics and reconfigurable logic," International Journal of Nanotechnology, vol. 7, no. 4/5/6/7/8 pp. 367 - 382, 2010.

Articles Published in Refereed International Conference Proceedings

  1. M. Keyser, R. Gauchi, P. -E. Gaillardon, "An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing," 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), Oct 3-5, 2022, Patras, Greece.

  2. C. Muscari Tomajoli, L. Collini, J. Bhandari, A. K. T. Moosa, B. Tan, X. Tang, P.-E. Gaillardon, R. Karri, C. Pilato, "ALICE: An Automatic Design Flow for eFPGA Redaction", DAC, July 10-14, 2022, San Francisco, CA, USA.

  3. W. Lau Neto, L. Amaru, V. Possani, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, "Improving LUT-Based Optimization for ASIC", DAC, July 10-14, 2022, , San Francisco, CA, USA.

  4. R. Gauchi, A. Snelgrove , P.-E. Gaillardon, "An Open-Source Three-Independent-Gate FET Standard Cell Library for Mixed Logic Synthesis", IEEE International Symposium of Circuits and Systems (ISCAS), May 28-June 1 2022, Austin, TX, USA.

  5. A. Snelgrove, P.-E. Gaillardon, "Programmable logic elements using multigate ambipolar transistors", 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, April 6-8 2022, Prague, Czech Republic.

  6. W. Lau Neto, M. Trevisan Moreira, Y. Li, L. Amaru, C. Yu, P.-E. Gaillardon, "SLAP: A Supervised Learning Approach for Priority Cuts Technology Mapping," 58th Design Automation Conference (DAC), 5-9 December 2021, San Francisco, CA, USA.

  7. S. Temple, A. Snelgrove, W. Lau Neto, P.-E. Gaillardon, "LSOracle 2.0: Capabilities, Integration, and Performance", Workshop on Open-Source EDA Technology (WOSET), November 4, Virtual.

  8. J. Bhandari, A. Khader, T. Moosa, B. Tan, C. Pilato, G. Gore, X. Tang, S. Temple, P.-E. Gaillardon, "Exploring eFPGA-based Redaction for IP Protection", ICCAD, 1-4 November 2021

  9. K. Kelly, A. Butterfield, E. Xing, K. Le, T. Sayahi, J. Moore, T. Becnel, M. Meyer, R. Whitaker, P.-E. Gaillardon, "Building an Aerosol Sensing Sensor Network and Inspiring Citizen Scientists", AAAR Conference, 18-22 October, 2021

  10. M. Couriol, E. Giacomin, P.-E. Gaillardon, "A 12 pA Sigma Delta ADC Topology for Chemiresistive Sensor-Based Application", VLSI-Soc, 4-8 Octobre 2021.

  11. M. Couriol, P. Cadareanu, E. Giacomin, P.-E. Gaillardon, "A Novel High-Gain Amplifier Circuit Using Super-Steep-Subthreshold-Slope Field-Effect Transistors", VLSI-Soc, 4-8 Octobre 2021.

  12. A. Snelgrove, S. Temple, P.-E. Gaillardon, "Structure Aware Partitioning for Mixed LogicSynthesis", IWLS, 19-21 July, 2021, Virtual.

  13. W. Lau Neto, M. Trevisan Moreira, Y. Li, L. Amaru, C. Yu, P.-E. Gaillardon, "A Supervised Learning Approach for Technology Mapping", IWLS, 19-21 July, 2021, Virtual.

  14. G. Brown, V. Tenace, P.E. Gaillardon, "NEMO-CNN: An Efficient Near-Memory Accelerator for Convolutional Neural Networks", ASAP, 7-8 July, 2021, Virtual.

  15. E. Giacomin, F. Catthoor, P.-E. Gaillardon, "Area-Efficient Multiplier Designs Using a 3D Nanofabric Process Flow," IEEE International Symposium on Circuits and Systems (ISCAS), 23-26 May 2021, Daegu, Korea.

  16. A. Alacchi, E. Giacomin, X. Tang, P.-E. Gaillardon, "Smart-Redundancy: an Alternative SEU/Set Mitigation Method for FPGAs," IEEE International Symposium on Circuits and Systems (ISCAS), 23-26 May 2021, Daegu, Korea.

  17. S. Temple, W. Lau Neto, M. Austin, X. Tang, P.-E. Gaillardon, "LSOracle: Open-source Mixed Logic Synthesis", Invited Paper, Government Microcircuit Applications & Critical Technology Conference (GOMACTech), March 29-April 1, 2021, Virtual

  18. G. Gore, X. Tang, P.-E. Gaillardon, "A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAs," International Symposium on Physical Design (ISPD), 21-24 March 2021, Virtual.

  19. S. Rai, W. Lau Neto, Y. Miyasaka, X. Zhang, M. Yu, Q. Y. M. Fujita, G. B. Manske, M. F. Pontes, L. S. da Rosa Junior, M. S. de Aguiar, P. F. Butzen, P.-C. Chien, Y.-S. Huang, H.-R. Wang, J.-H. R. Jiang, J. Gu, Z. Zhao, Z. Jiang, D. Z. Pan, B. A. de Abreu, I. S. Campos, A. Berndt, C. Meinhardt, J. T. Carvalho, M. Grellert, S. Bampi, A. Lohana, A. Kumar, W. Zeng, A. Davoodi, R. O. Topaloglu, Y. Zhou, J. Dotzel, Y. Zhang, H. Wang, Z. Zhang, V. Tenace, P.-E. Gaillardon, A. Mishchenko, S. Chatterjee, "Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization," Design, Automation and Test in Europe (DATE), 1-5 February 2021, Virtual.

  20. T. Becnel, P.-E. Gaillardon, "A Deep Learning Approach of Sensor Fusion Inference at the Edge," Design, Automation and Test in Europe (DATE), 1-5 February 2021, Virtual.

  21. W. Lau Neto, M. Trevisan Moreira, L. Amaru, C. Yu, P.-E. Gaillardon, "Read your Circuit: Leveraging Word Embedding to Guide Logic Optimization," 26nd Asia and South Pacific Design Automation Conference (ASP-DAC), 18-21 January 2021, Tokyo, Japan.

  22. S. Temple, W. Lau Neto, M. Austin, X. Tang, P.-E. Gaillardon, "LSOracle: Using Mixed Logic Synthesis in an Open Source ASIC Design Flow," Workshop on Open-Source EDA Technology, 2020 (WOSET), 5 November 2020, Virtual. Honorable mention for best contribution award. Honorable mention for best video award.

  23. X. Tang, G. Gore, E. Giacomin, A. Alacchi, B. Chauviere, P.-E. Gaillardon, "OpenFPGA: Towards Automated Prototyping for Versatile FPGAs," Workshop on Open-Source EDA Technology, 2020 (WOSET), 5 November 2020, Virtual. Best contribution award. Honorable mention for best video award.

  24. E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, P.-E. Gaillardon, "Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow," 28th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 5-7 October 2020, Salt Lake City, UT, USA.

  25. J. Moore, K. Kelly, K. My Quyen, P. Goffin, A. Butterfield, J. Wiese, T. Becnel, M. Dailey, P.-E. Gaillardon, "Engaging Pre-College Students in Hypothesis Generation using a Citizen Scientist Network of Air Quality Sensors," 2020 ASEE Annual Conference & Exposition, 21-24 June 2020, Montreal, UT, Canada.

  26. S. Narayanan, K. Taht, R. Balasubramonian, E.Giacomin, P.-E. Gaillardon, "An Architecture and Dataflow Tailored for Spiking Neural Networks," 47th International Symposium on Computer Architecture (ISCA), May 30 - June 4, Valencia, Spain.

  27. M. Austin, W. Lau Neto, S. Temple, L. Amaru, X. Tang, P.-E. Gaillardon, "A Scalable Mixed Synthesis Framework for Heterogeneous Networks," Design, Automation and Test in Europe (DATE), Interactive presentation, 9-13 March 2020, Grenoble, France.

  28. X. Tang, E. Giacomin, P. Cadareanu, G. Gore, P.-E. Gaillardon, "A RRAM-based FPGA for Energy-efficient Edge Computing," Design, Automation and Test in Europe (DATE), Invited paper, 9-13 March 2020, Grenoble, France.

  29. M. M. Sharifi, R. Rajaei, P. Cadareanu, P.-E. Gaillardon, Y. Jin, M. Niemier, X. S. Hu, "A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel Attacks," Design, Automation and Test in Europe (DATE), 9-13 March 2020, Grenoble, France.

  30. X. Tang, E. Giacomin, A. Alacchi, P.-E. Gaillardon, "A Study on Switch Block Patterns for Tileable FPGA Routing Architectures," 2019 International Conference on Field Programmable Technology (FPT), 9-13 December 2019, Tianjin, China.

  31. W. Lau Neto, M. Austin, S. Temple, L. Amaru, X. Tang, P.-E. Gaillardon, "LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence," Invited paper, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 4-7 November 2019, Westminster, CO, USA.

  32. A. Levisse, M. Rios, W. Simon, P.-E. Gaillardon, D. Atienza Alonso, "Functionality Enhanced Memories for Edge-AI Embedded Systems," Invited paper, Non-Volatile Memory Technology (NVMTS) Symposium 2019, October 28-30, 2019, Durham, NC, USA.

  33. P. Cadareanu, P.-E. Gaillardon, "Nanoscale Three-Independent-Gate Transistors: Geometric TCAD Simulations at the 10 nm-Node," IEEE Nanotechnology Materials Devices Conference, 27-30 October 2019, Stockholm, Sweden.

  34. A. Nag, C.N. Ramachandr, R. Balasubramonian, R. Stutsman, E. Giacomin, H. Kambalasubramanyam, P.-E. Gaillardon "GenCache: Leveraging In-Cache Operators for Efficient Sequence Alignment," 52nd IEEE/ACM International Symposium on Microarchitecture, 12-16 October 2019, Columbus, OH, USA.

  35. S. Gudaparthi, S. Narayanan, R. Balasubramonian, E. Giacomin, H. Kambalasubramanyam, P.-E. Gaillardon "Wire-Aware Architecture and Dataflow for CNN Accelerators," 52nd IEEE/ACM International Symposium on Microarchitecture, 12-16 October 2019, Columbus, OH, USA.

  36. J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, P.-E. Gaillardon, "A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories," 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6-9 October 2019, Cusco, Peru.

  37. G. Gore, P. Cadareanu, E. Giacomin, P.-E. Gaillardon, "A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors," 27th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 6-9 October 2019, Cusco, Peru.

  38. X. Tang, E. Giacomin, A. Alacchi, B. Chauviere, P.-E. Gaillardon, "OpenFPGA: An Opensource Framework Enabling Rapid Prototyping of Customizable FPGAs," 29th International Conference on Field-programmable Logic and Applications (FPL), 9-13 September 2019, Barcelona, Spain.

  39. W. Lau Neto, X. Tang, M. Austin, L. Amaru, P.-E. Gaillardon, "Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 15-17 July 2019, Miami, FL, USA.

  40. M. Austin, W. Lau Neto, L. Amaru, X. Tang and P.-E. Gaillardon, "Towards a Novel Logic Synthesis Framework Supervised by Convolutional Neural Network," 28th International Workshop on Logic & Synthesis (IWLS), 21-23 June 2019, Lausanne, Switzerland.

  41. W. Lau Neto, M. Austin, L. Amaru, X. Tang and P.-E. Gaillardon, "Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs," 28th International Workshop on Logic & Synthesis (IWLS), 21-23 June 2019, Lausanne, Switzerland.

  42. T. Becnel, T. Sayahi, K. Kelly, P.-E. Gaillardon, "A Recursive Least Squares Approach to Partially Blind Calibration of a Pollution Sensor Network," 15th IEEE International Conference on Embedded Software and Systems (ICESS), 2-3 June 2019, Las Vegas, NV, USA.

  43. T. Greenberg-Toledo, E. Giacomin, S. Kvatinsky, P.-E. Gaillardon, "A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications," IEEE International Symposium on Circuits and Systems (ISCAS), 26-29 May 2019, Sapporo, Japan.

  44. P. Cadareanu, N. Reddy C, C. G. Almudever, A. Khanna, A. Parihar, A. Raychowdhury, S., K.Bertels, V. Narayanan, M. Di Ventra P.-E. Gaillardon, "Rebooting Our Computing Models," Design, Automation and Test in Europe (DATE), Invited paper, 25-29 March 2019, Florence, Italy.

  45. E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P.-E. Gaillardon, G. De Micheli, "Scalable Boolean Methods In A Modern Synthesis Flow," Proceedings of the Design, Automation and Test in Europe (DATE), 25-29 March 2019, Florence, Italy.

  46. X. Tang, E. Giacomin, Natan Chetrit, P.-E. Gaillardon, "Ultra-low-power RRAM-based FPGA: A Road towards Reconfigurable Edge Computing," Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 25-28 March 2019, Albuquerque, NM, USA.

  47. J. Romero-Gonzalez, P.-E. Gaillardon, "An Efficient Adder Architecture with Three-Independent-Gate Field-Effect Transistors," IEEE International Conference on Rebooting Computing (ICRC), 7-9 November 2018, Tysons, VA, USA.

  48. S. Rai, S. Srinivasa, P. Cadareanu, X. Yin, X. Sharon Hu, P.-E. Gaillardon, V. Narayanan, A. Kumar, "Emerging Reconfigurable Nanotechnologies: Can they support Future Electronics?," Invited Paper, IEEE 2018 International Conference On Computer Aided Design, 5-8 November 2018, San Diego, CA, USA.

  49. E. Giacomin, P.-E. Gaillardon, "Differential Power Analysis Mitigation Technique Using Three-Independent-Gate Field Effect Transistors," 26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 8-10 October 2018, Verona, Italy.

  50. G. Resta, Y. Balaji, D. Lin, I. P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, "Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors," 76th annual Device Research Conference (DRC), 24-27 June 2018, Santa Barbara, CA, USA.

  51. A. Butterfield, K. My Quyen, K. Kelly, P. Goffin, T. Becnel, P.-E. Gaillardon, "Citizen Scientists Engagement in Air Quality Measurements," 2018 ASEE Annual Conference & Exposition, 24-27 June 2018, Salt Lake City, UT, USA.

  52. G. Resta, J. Romero-Gonzalez, Y. Balaji, T. Agarwal, D. Lin, F. Catthor, I. P. Radu, G. De Micheli, P.-E. Gaillardon, "Towards high-performance polarity-controllable FETs with 2D materials," Design, Automation, and Test in Europe (DATE), 19-23 March 2018, Dresden, Germany.

  53. N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P.-E. Gaillardon, S. Kvatinsky, "Practical Challenges in Delivering the Promises of Read Processing-in-Memory Machines," Design, Automation, and Test in Europe (DATE), 19-23 March 2018, Dresden, Germany.

  54. L. Amarú, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, P.-E. Gaillardon, J. Olson, R. Brayton, G. De Micheli, "Enabling Exact Delay Synthesis," IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 13-16 November 2017, Irvine, CA, USA.

  55. J. Reuben, R. Ben Hur, N. Wald, N. Talati, P.-E. Gaillardon, S. Kvatinsky, "Memristive Logic: A Framework for Evaluation and Comparison," 27th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS), 25-27 September 2017, Thessaloniki, Greece.

  56. E. Giacomin, J. Romero-Gonzalez, P.-E. Gaillardon, "Low-Power Multiplexer Designs Using Three-Independent-Gate Field Effect Transistors," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 25-26 July 2017, Newport, RI, USA.

  57. G. Meuli, M. Soeken, P.-E. Gaillardon, G. De Micheli, "A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing," 26th International Workshop on Logic & Synthesis (IWLS), 17-18 June 2017, Austin, TX, USA.

  58. M. Nataraj, A. Levisse, B. Giraud, J.-P. Noel, P. Meinerzhagen, J.M. Portal, P.-E. Gaillardon, "Design Methodology for Area and Energy Efficient OxRAM-Based Non-Volatile Flip-Flop," IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MA, USA.

  59. I. Tzouvadaki, S. Naus, P.-E. Gaillardon, A. Biscontini, G. De Micheli, S. Carrara, "An Efficient Electronic Measurement Interface for Memristive Biosensors," IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA.

  60. E. Giacomin, X. Tang, G. De Micheli, P.-E. Gaillardon, "Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(Ram) Programming Structure," TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA.

  61. X. Tang, G. Kim, P.-E. Gaillardon, G. De Micheli, "A Study on the Programming Structures for RRAM-Based FPGA Architectures," TCAS presentation, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA.

  62. M. Soeken, P.-E. Gaillardon, G. De Micheli, "RM3 Based Logic Synthesis," Invited Paper, IEEE International Symposium on Circuits and Systems (ISCAS), 28-31 May 2017, Baltimore, MD, USA.

  63. Z. Chu, X. Tang, M. Soeken, A. Petkovska, G. Zgheib, L. Amarú, Y. Xia, P. Ienne, G. De Micheli, P.-E. Gaillardon, "Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains," 27th Great Lakes Symposium on VLSI (GLSVLSI), 10-12 May 2017, Banff, Alberta, Canada.

  64. S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, G. De Micheli, R. Drechsler, "Endurance Management for Resistive Logic-In-Memory Computing Architectures," Design, Automation & Test in Europe Conference (DATE), 27-31 March 2017, Lausanne, Switzerland.

  65. X. Tang, E. Giacomin, G. De Micheli, P.-E. Gaillardon, "Physical Design Considerations of One-level RRAM-based Routing Multiplexers," International Symposium on Physical Design (ISPD), 19-22 March 2017, Portland, OR, USA.

  66. X. Tang, G. De Micheli, P.-E. Gaillardon, "Optimization Opportunities in RRAM-based FPGA Architectures," IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), 20-23 February 2017, Bariloche, Argentina.

  67. L. Amarú, M. Soeken, W. Haaswijk, E. Testa, P. Vuillod, J. Luo, P.-E. Gaillardon, G. De Micheli, "Multi-level Logic Benchmarks: An Exactness Study," 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 16-19 January 2017, Chiba, Japan.

  68. W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, "A Novel Basis for Logic Rewriting," 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), 16-19 January 2017, Chiba, Japan.

  69. M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, "Perspectives of Multiple-Independent-Gate Field Effect Transistors for Efficient Terahertz Detection Applications," SPIE Terahertz Emitters, Receivers, and Applications VII, 28 August-1 September 2016, San Francisco, CA, USA.

  70. E. Testa, M. Soeken, O. Zografos, L. Amarú, P. Raghavan, R. Lauwereins, P.-E. Gaillardon, G. De Micheli, "Inversion Optimization in Majority-Inverter Graphs," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 18-20 July 2016, Beijing, China.

  71. M. Hasan, P.-E. Gaillardon, B. Sensale-Rodriguez, "A Compact DC Model for Dual-Independent-Gate FinFETs," 74th annual Device Research Conference (DRC), 19-22 June 2016, Newark, DE, USA.

  72. E. Testa, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, "Inversion Minimization in Majority-Inverter Graphs," 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA.

  73. W. Haaswijk, M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, "LUT Mapping and Optimization for Majority-Inverter Graphs," 25th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA.

  74. M. Soeken, S. Shirinzadeh, P.-E. Gaillardon, L. Amarú, R. Drechsler, G. De Micheli, "An MIG-based Compiler for Programmable Logic-in-Memory Architectures," 53rd Design Automation Conference (DAC), 5-9 June 2016, Austin, TX, USA.

  75. A. Chattopadhyay, L. Amarú, M. Soeken, P.-E. Gaillardon, G. De Micheli, "Notes on Majority Boolean Algebra," IEEE International Symposium on Multi-Valued Logic (ISMVL), 18-20 May 2016, Sapporo, Japan.

  76. P.-E. Gaillardon, M. Hasan, A. Saha, L. Amarú, R. Walker, B. Sensale-Rodriguez, "Digital, Analog and RF Design Opportunities of Three-Independent-Gate Transistors," Invited Paper, IEEE International Symposium on Circuits and Systems (ISCAS), 22-25 May 2016, Montreal, Canada.

  77. P.-E. Gaillardon, R. Magni, L. Amarú, M. Hasan, R. Walker, B. Sensale-Rodriguez, J.-F. Christmann, E. Beigné, "Three-Independent-Gate Transistors: Opportunities in Digital, Analog and RF Applications," Invited Paper, IEEE Latin-American Test Symposium (LATS), 6-8 April 2016, Foz de Iguaçu, Brazil.

  78. S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, "Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs," Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany.

  79. M. Soeken, P.-E. Gaillardon, L. Amarú, G. De Micheli, "Optimizing Majority-Inverter Graphs With Functional Hashing," Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany.

  80. L. Amarú, P.-E. Gaillardon, R. Wille, G. De Micheli, "Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking," Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany.

  81. P.-E. Gaillardon, L. Amarú, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, "The Programmable Logic-in-Memory (PLiM) Computer," Invited Paper, Design, Automation & Test in Europe Conference (DATE), 14-18 March 2016, Dresden, Germany.

  82. K. Shamsi, P.-E. Gaillardon, Y. Jin, "Hardware Platform Protection Using Emerging Memory Technologies," Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA.

  83. P.-E. Gaillardon, R. Walker, B. Sensale-Rodriguez, "Breakthroughs in Analog and RF Circuit Performance through Steep-Slope FinFETs," Government Microcircuit Applications & Critical Technology Conference (GOMACTech), 14-17 March 2016, Orlando, FL, USA.

  84. X. Tang, P.-E. Gaillardon, G. De Micheli, "A Full-Capacity Local Routing Architecture for FPGAs," Abstract, 24th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 21-23 February 2016, Monterey, CA, USA.

  85. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Majority-based Synthesis for Nanotechnologies," Invited Paper, 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 25-28 January 2016, Macao, China.

  86. I. P. Radu, O. Zografos, A. Vaysset, F. Ciubotaru, J. Yan, J. Swerts, D. Radisic, B. Briggs, B. Soree, M. Manfrini, M. Ercken, C. Wilson, P. Raghavan, C. Adelmann, A. Thean, L. Amarú, P.-E. Gaillardon, G. De Micheli, D. E. Nikonov, S. Manipatruni, I. A. Young, "Spintronic Majority Gates," Invited Paper, IEEE International Electron Devices Meeting (IEDM), 07-09 December 2015, Washington (DC), USA.

  87. X. Tang, P.-E. Gaillardon, G. De Micheli, "FPGA-SPICE: A Simulation-based Power Estimation Framework for FPGAs," 33rd IEEE International Conference on Computer Design (ICCD), 18-21 October 2015, New York City, USA.

  88. K. Shamsi, Y. Bi, Y. Jin, P.-E. Gaillardon, M. Niemier, X. S. Hu, "Reliable and High Performance STT-MRAM Architectures based on Controllable-Polarity Devices," 33rd IEEE International Conference on Computer Design (ICCD), 18-21 October 2015, New York City, USA.

  89. J. Zhang, P.-E. Gaillardon, G. De Micheli, "A Surface Potential and Current Model for Polarity-Controllable Silicon Nanowire FETs," 45th European Solid-State Device Conference (ESSDERC), 14-18 September 2015, Graz, Austria.

  90. P.-E. Gaillardon, J. Zhang, M. De Marchi, G. De Micheli, "Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors," Invited Paper, 10th IEEE Nanotechnology Materials and Devices Conference (NMDC), 13-16 September 2015, Anchorage, USA.

  91. X. Tang, P.-E. Gaillardon, G. De Micheli, "Accurate Power Analysis for Near-Vt RRAM-based FPGA," 25th International Conference on Field-programmable Logic and Applications (FPL), 2-4 September 2015, London, UK.

  92. O. Zografos, B. Sorée, A. Vaysset, S. Cosemans, L. Amarú, P.-E. Gaillardon, G. De Micheli, R. Lauwereins, S. Sayan, P. Raghavan, I. Radu, A. Thean, "Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS," 15th International IEEE Conference on Nanotechnology (NANO), 27-30 July 2015, Rome, Italy.

  93. H. Ghasemzadeh, P.-E. Gaillardon, J. Zhang, M. Sonza Reorda, E. Sanchez, G. De Micheli, "On the Design of Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 8-10 July 2015, Montpellier, France.

  94. L. Amarú, P.-E. Gaillardon, A. Mishchenko, M. Ciesielski, G. De Micheli, "Exploiting Circuit Duality to Speed Up SAT," IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 8-10 July 2015, Montpellier, France.

  95. W. Haaswijk, L. Amarú, P.-E. Gaillardon, G. De Micheli, "Unlocking NEM Relays Design Opportunities with Biconditional Binary Decision Diagrams," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 8-10 July 2015, Boston, MA, USA.

  96. L. Amarú, P.-E. Gaillardon, G. De Micheli, "The EPFL Combinational Benchmark Suite," 24th International Workshop on Logic & Synthesis (IWLS), 12-15 June 2015, Mountain View, CA, USA.

  97. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Boolean Logic Optimization in Majority-Inverter Graphs," 52nd Design Automation Conference (DAC), 7-11 June 2015, San Francisco, CA, USA.

  98. A. Chattopadhyay, A. Littarru, L. Amarú, P.-E. Gaillardon, G. De Micheli, "Reversible Logic Synthesis via Biconditional Binary Decision Diagrams," IEEE International Symposium on Multi-Valued Logic (ISMVL), 18-20 May 2015, Waterloo, ON, Canada.

  99. S. Miryala, V. Tenace, A. Calimera, E. Macii, M. Poncino, L. Amarú, G. De Micheli, P.-E. Gaillardon, "Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization," 25th Great Lakes Symposium on VLSI (GLSVLSI), 20-22 May 2015, Pittsburgh, PA, USA.

  100. L. Amarú, A. Petkovska, P.-E. Gaillardon, D. Novo Bruna, P. Ienne, G. De Micheli, "Majority-Inverter Graph for FPGA Synthesis," 19th Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI), 16-17 March 2015, Yilan, Taiwan.

  101. P.-E. Gaillardon, X. Tang, J. Sandrini, M. Thammasack, S. Rahimian Omam, D. Sacchetto, Y. Leblebici, G. De Micheli, "A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs," Invited Paper, Design, Automation & Test in Europe Conference (DATE), 9-13 March 2015, Grenoble, France.

  102. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "Fault Modeling in Controllable-Polarity Silicon Nanowire Circuits," Design, Automation & Test in Europe Conference (DATE), 9-13 March 2015, Grenoble, France.

  103. S. Rahimian Omam, X. Tang, P.-E. Gaillardon, G. De Micheli, "A Study on Buffer Distribution for RRAM-based FPGA Structure," IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 24-27 February 2015, Montevideo, Uruguay.

  104. J. Broc, L. Amarú, J. Joven Murillo, P.-E. Gaillardon, K. Palem, G. De Micheli, "A Fast Pruning Technique for Low-Power Inexact Circuit Design," IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 24-27 February 2015, Montevideo, Uruguay.

  105. P.-E. Gaillardon, G. Kim, X. Tang, L. Amarú, G. De Micheli, "Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion," Abstract, 23rd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 22-24 February 2015, Monterey, CA, USA.

  106. L. Amarú, G. Hills, P.-E. Gaillardon, S. Mitra, G. De Micheli, "Multiple Independent Gate FETs: How Many Gates Do We Need?," 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 19-22 January 2015, Chiba, Japan.

  107. J. Zhang, M. De Marchi, P.-E. Gaillardon, G. De Micheli, "A Schottky-Barrier Silicon FinFET with 6.0mV/dec Subthreshold Slope over 5 Decades of Current," International Electron Devices Meeting (IEDM), 15-17 December 2014, San Francisco, CA, USA.

  108. X. Tang, P.-E. Gaillardon, G. De Micheli, "A High-Performance Low-Power Near-Vt RRAM-based FPGA," International Conference on Field-Programmable Technology (FPT), 10-12 December 2014, Shanghai, China. BEST PAPER CANDIDATE

  109. Y. Bi, P.-E. Gaillardon, X. S. Hu, M. Niemier, J.-S. Yuan Y. Jin, "Leveraging Emerging Technology for Hardware Security – Case Study on Silicon Nanowire FETs and Graphene SymFETs," 23rd Asian Test Symposium (ATS), 16-19 November 2014, Hangzhou, China.

  110. J. Sandrini, A. Cevrero, T. Demirci, P.-E. Gaillardon, D. Sacchetto, G. De Micheli, Y. Leblebici, "Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip," 40th International Micro and Nano Engineering Conference (MNE), 22-26 September 2014, Lausanne, Switzerland.

  111. X. Tang, P.-E. Gaillardon, G. De Micheli, "Pattern-Based FPGA Logic Block and Clustering Algorithm," 24th International Conference on Field Programmable Logic and Applications (FPL), 2-4 September 2014, München, Germany.

  112. O. Zografos, L. Amarú, P.-E. Gaillardon, P. Raghavan, G. De Micheli, "Majority Logic Synthesis for Spin Wave Technology," 17th Euromicro Conference on Digital Systems Design (DSD), 27-29 August 2014, Verona, Italy.

  113. P.-E. Gaillardon, L. Amarú, G. De Micheli, "Unlocking Controllable-Polarity Transistors Opportunities by Exclusive OR and Majority Logic Synthesis," Invited Paper, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 9-11 July 2014, Tampa, FL, USA.

  114. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 8-10 July 2014, Paris, France.

  115. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization," 51st Design Automation Conference (DAC), 1-5 June 2014, San Francisco, CA, USA.

  116. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Majority Logic Representation and Satisfiability," 23rd International Workshop on Logic & Synthesis (IWLS), 30 May-1 June 2014, San Francisco, CA, USA.

  117. X. Tang, J. Zhang, P.-E. Gaillardon, G. De Micheli, "TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs," IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June 2014, Melbourne, Australia.

  118. O. Zografos, P.-E. Gaillardon, G. De Micheli, "Novel Grid-Based Power Routing Scheme for Regular Controllable-Polarity FET Arrangements," IEEE International Symposium on Circuits and Systems (ISCAS), 1-5 June 2014, Melbourne, Australia.

  119. P.-E. Gaillardon, X. Tang, G. De Micheli, "Novel Configurable Logic Block Architecture Exploiting Controllable-Polarity Transistors," Invited Paper, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), 26-28 May 2014, Montpellier, France.

  120. F. Clermidy, O. Turkyilmaz, O. Billoint, P.-E. Gaillardon, "3D technologies for reconfigurable architectures," Invited Paper, 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), 26-28 May 2014, Montpellier, France.

  121. P.-E. Gaillardon, L. Amarú, J. Zhang, G. De Micheli, "Advanced System on a Chip Design Based on Controllable-Polarity FETs," Invited Paper, Design, Automation & Test in Europe Conference (DATE), 10-14 March 2014, Dresden, Germany.

  122. L. Amarú, P.-E. Gaillardon, G. De Micheli, "An Efficient Manipulation Package for Biconditional Binary Decision Diagrams," Design, Automation & Test in Europe Conference (DATE), 10-14 March 2014, Dresden, Germany.

  123. P.-E. Gaillardon, L. Amarú, G. De Micheli, "A New Basic Logic Structure for Data-Path Computation," Abstract, 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 26-28 February 2014, Monterey, CA, USA.

  124. L. Amarú, P.-E. Gaillardon, A. Burg, G. De Micheli, "Data Compression via Logic Synthesis," 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 20-23 January 2014, Singapore.

  125. H. Ghasemzadeh, P.-E. Gaillardon, M. Yazdani, G. De Micheli, "A Fast TCAD-based Methodology for Variation Analysis of Emerging Nano-devices," 26th IEEE Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), 2-4 October 2013, New York City, NY, USA.

  126. C. Gasnier, P.-E. Gaillardon, G. De Micheli, "SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 15-17 July 2013, New York City, NY, USA. BEST PAPER CANDIDATE

  127. I. Kazi, P. Meinerzhagen, P.-E. Gaillardon, D. Sacchetto, A. Burg, G. De Micheli, "A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write," 11th IEEE International New Circuits and Systems Conference (NEWCAS), 16-19 June 2013, Paris, France.

  128. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs," Invited Paper, 11th IEEE International New Circuits and Systems Conference (NEWCAS), 16-19 June 2013, Paris, France.

  129. L. Amarú, P.-E. Gaillardon, G. De Micheli, "BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Decomposition," 50th Design Automation Conference (DAC), 2-6 June 2013, Austin, TX, USA.

  130. P.-E. Gaillardon, M. De Marchi, D. Sacchetto, S. Bobba, L. Amarú, Y. Leblebici, G. De Micheli, "Towards Structured ASICs using Polarity-Tunable Si Nanowire Transistors," Invited Paper, 50th Design Automation Conference (DAC), 2-6 June 2013, Austin, TX, USA.

  131. J. Zhang, P.-E. Gaillardon, G. De Micheli, "Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs," IEEE International Symposium on Circuits and Systems (ISCAS), 19-23 May 2013, Beijing, China.

  132. O. Turkyilmaz, L. Amarú, F. Clermidy, P.-E. Gaillardon, G. De Micheli, "Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET," IEEE International Symposium on Circuits and Systems (ISCAS), 19-23 May 2013, Beijing, China.

  133. S. Bobba, P.-E. Gaillardon, C. Seiculescu, V. Pavlidis, G. De Micheli, "3.5-D Integration: A Case Study," IEEE International Symposium on Circuits and Systems (ISCAS), 19-23 May 2013, Beijing, China.

  134. P.-E Gaillardon, H. Ghasemzadeh, G. De Micheli, "Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: a Robustness Study," Invited Paper, Latin American Test Workshop (LATW), 2-5 April 2013, Cordoba, Argentina.

  135. P.-E. Gaillardon, S. Bobba, L. Amarú, M. De Marchi, D. Sacchetto, Y. Leblebici, G. De Micheli, "Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs", Invited Paper, Design, Automation & Test in Europe Conference (DATE), 18-22 March 2013, Grenoble, France.

  136. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Biconditional BDD: A New Canonical BDD for Logic Synthesis targeting Ambipolar Transistors", Design, Automation & Test in Europe Conference (DATE), 18-22 March 2013, Grenoble, France.

  137. L. Amarú, P.-E. Gaillardon, G. De Micheli, "MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits," IEEE/ACM 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 22-25 January 2013, Yokohama, Japan. BEST PAPER CANDIDATE

  138. M. De Marchi, D. Sacchetto, S. Frache, J. Zhang, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs," International Electron Devices Meeting (IEDM), 10-12 December 2012, San Francisco, CA, USA. APPEAR in the IEDM PRESS KIT and HIGHLIGHTED by Science Magazine (21 June 2013)

  139. P.-E. Gaillardon, D. Sacchetto, S. Bobba, Y. Leblebici, G. De Micheli, "GMS: Generic Memristive Structure for Non-Volatile FPGAs," Invited Paper, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 07-10 October 2012, Santa Cruz, CA, USA.

  140. S. Bobba, P.-E. Gaillardon, J. Zhang, M. De Marchi, D. Sacchetto, Y. Leblebici, G. De Micheli "Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 04-06 July 2012, Amsterdam, The Netherlands. BEST PAPER AWARD.

  141. P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, B. Sklenard, P. Coudrain, S. Bobba, H. Ben Jamaa, P.-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot, T. Poiroux, "Advances, Challenges and Opportunities in 3D CMOS Sequential Integration," Invited Paper, IEEE International Electron Devices Meeting (IEDM), 05-07 December 2011, Washington, DC, USA.

  142. P. Batude, T. Ernst, J. Arcamone, P. Coudrain, P.-E. Gaillardon, "3D sequential integration: a key enabling technology for heterogeneous co-integration of new function with CMOS," IEEE Circuits and Systems Society Forum on Emerging and Selected Topics (CAS-FEST), 20 May 2012, Seoul, South Korea.

  143. P.-E. Gaillardon, M. H. Ben Jamaa, F. Clermidy, I. O’Connor, "Ultra-Fine Grain FPGAs: A Granularity Study," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 08-09 June 2011, San Diego, CA, USA.

  144. S. Onkaraiah, P.-E. Gaillardon, M. Reyboz, F. Clermidy, J.-M. Portal, M. Bocquet, C. Muller, "Using OxRRAM Memories for Improving Communications of Reconfigurable FPGA Architectures," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), 08-09 June 2011, San Diego, CA, USA.

  145. P.-E. Gaillardon, M. H. Ben Jamaa, P.-H. Morel, J.-P. Noël, F. Clermidy, I. O'Connor, "Can We Go Towards True 3-D Architectures?," WACI session, 48th Design Automation Conference (DAC), 5-10 June 2011, San Diego, CA, USA.

  146. P.-E. Gaillardon, M. H. Ben Jamaa, F. Clermidy, I. O'Connor, "Evaluation of a Crossbar Multiplexer in a Lithography-Based Nanowire Technology," IEEE International Symposium on Circuits and Systems (ISCAS), 15-18 May 2011, Rio de Janeiro, Brazil.

  147. P.-E. Gaillardon, M. H. Ben Jamaa, G. Betti Beneventi, F. Clermidy, L. Perniola, "Emerging Memory Technologies for Reconfigurable Routing in FPGA Architecture," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 12-15 December 2010, Athens, Greece.

  148. I. O'Connor, K. Jabeur, D. Navarro, N. Yakymets, P.-E. Gaillardon, M. H. Ben Jamaa, F. Clermidy, "Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 12-15 December 2010, Athens, Greece.

  149. P.-E. Gaillardon, M. Haykel Ben Jamaa, M. Reyboz, G. Betti Beneventi, F. Clermidy, L. Perniola, I. O’Connor, "Phase-Change-Memory-Based Storage Elements for Configurable Logic," International Conference on Field-Programmable Technology (FPT), 8-10 December 2010, Beijing, China.

  150. K. Jabeur, P.-E. Gaillardon, D. Navarro, I. O'Connor, M. H. Ben Jamaa, F. Clermidy, "Reducing transistor count in clocked standard cells with ambipolar double-gate FETs," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), June 17-18 2010, Anaheim, CA, USA.

  151. P.-E. Gaillardon, F. Clermidy, I. O'Connor, R. Daviot, "Reconfigurable Reconfigurable nanoscale logic cells: a comparison study," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13-16 December 2009, Hammamet, Tunisia.

  152. P.-E. Gaillardon, I. O'Connor, J. Liu, F. Clermidy, R. Daviot, "Mapping method of reconfigurable cell matrices based on nanoscale devices using inter-stage fixed interconnection scheme," IEEE International Conference on Electronics, Circuits and Systems (ICECS), 13-16 December 2009, Hammamet, Tunisia.

  153. P.-E. Gaillardon, I. O'Connor, J. Liu, F. Clermidy, "Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices," IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), July 30-31 2009, San Francisco, CA, USA.

Patents

  1. P.-E. Gaillardon, T. Becnel, "3-Branch Deep Neural Network", United States patent application US 17/592,230, March 2022.

  2. P.-E. Gaillardon, E. Giacomin, J. Vieira, "Digital rram-based convolutional block," United States patent application US20200098428A1. 26, March, 2020.

  3. P.-E. Gaillardon, L. Amarú, G. De Micheli, "Majority Logic Synthesis," United States patent US10394988B2. 27, August, 2019.

  4. P.-E. Gaillardon, X. Tang, G. Kim, G. De Micheli, E. Giacomin, "Resistive Random Access Memory Based Multiplexers and Field Programmable Gate Arrays," United States patent US10348306B2. 9 July 2019.

  5. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Boolean Logic Optimization in Majority-Inverter Graphs," United States patent US10380309B2. 13 August 2018.

  6. X. Tang, P.-E. Gaillardon, G. De Micheli, "Pattern-Based FPGA Logic Block and Clustering Algorithm," United States patent US9971862B2. 15 May 2018.

  7. D. Sacchetto, S. Bobba, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, T. Demirci, "Resistive Switching Element and Use Thereof," United States patent US9412940B2. 9 August 2016.

  8. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Method for Speeding Up Boolean Satisfiability," United States patent US9685959B2. 20 June 2016.

  9. P.-E. Gaillardon, X. Tang, G. De Micheli, "High-performance low-power near-Vt resistive memory-based FPGA," United States patent US9130568B2. 1 March 2016.

  10. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Controllable Polarity FET based Arithmetic and Differential Logic," United States patent US9130568B2. 8 September 2015.

  11. P.-E. Gaillardon, G. Betti Beneventi, L. Perniola, "Memory cell," United States patent US8861254B2. 14 October 2014.

  12. P.-E. Gaillardon, F. Clermidy, I. O'Connor, P.-H. Morel, "Reconfigurable Boolean Cells having a Criss-crossed Nanowire Matrix," WIPO patent, WO2011070164A1. 16 June 2011.

Books

  1. P.-E. Gaillardon, "Functionality-Enhanced Devices: An alternative to Moore’s Law," Edited Book, The Institution of Engineering and Technology, ISBN 978-1-78561-558-0, 10 December 2018.

  2. P.-E. Gaillardon, "Reconfigurable Logic: Architecture, Tools and Applications," Edited book, Part of the "Devices, Circuits, and Systems Series" (Ed.: K. Iniewski), CRC press, 28 October 2015.

  3. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Disruptive Logic Architectures and Technologies: From Device to System Level," Springer, ISBN 978-1461430575, 24 April 2012.

Book Chapters

  1. E. Giacomin, J. Bömmels, J. Ryckaert, F. Catthoor, P.-E. Gaillardon, " 3D Nanofabric: Layout Challenges and Solutions for Ultra-Scaled Logic Designs," VLSI-SoC: Design Trends, Springer International Publishing, 2021.

  2. M. Thammasack, G. De Micheli, P.-E. Gaillardon, "Effect of O2- migration in Pt/HfO2/Ti/Pt structure," Resistive Switching: Oxide Materials, Mechanisms, Devices and Operations (Ed.: Rupp, Jennifer, Ielmini, Daniele, Valov, Ilia), Electronic Materials: Science & Technology, 2021.

  3. P. Cadareanu, G. Gore, E. Giacomin, P.-E. Gaillardon, "A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors," VLSI-SoC: New Technology Enabler, pp 307-322, Springer International Publishing, 2020.

  4. J. Vieira, E. Giacomin, Y. Mahmood Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, P.-E. Gaillardon, "Accelerating Inference on Binary Neural Networks with Digital RRAM Processing," VLSI-SoC: New Technology Enabler, pp 257-278, Springer International Publishing, 2020.

  5. J. Reuben, N. Talati, N. Wald, R. Ben-Hur, A. Haj Ali, P.-E. Gaillardon, "A Taxonomy and Evaluation Framework for Memristive Logic," Handbook of Memristor Networks, Springer, pp. 1065-1099, 2019.

  6. D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Memory Effects in Multi-Terminal solid state devices and their Applications," Handbook of Memristor Networks, Springer, pp. 1021-1064, 2019.

  7. G. V. Resta, I. P. Radu, G. De Micheli, P.-E. Gaillardon, "WSe2 polarity-controllable devices," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 71-90, 2018.

  8. J. Romero Gonzalez, P.-E. Gaillardon, "Three-Independent Gate FET’s Super Steep Subthreshold Slope," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 107-128, 2018.

  9. M. Hasan, R. Walker, P.-E. Gaillardon, B. Sensale-Rodriquez, "Super Sensitive Terahertz Detectors," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 129-146, 2018.

  10. O. Zografos, P.-E. Gaillardon, G. De Micheli, "Physical design of polarity controllable transistors," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 189-220, 2018.

  11. J. Romero Gonzalez, P.-E. Gaillardon, "BCB Benchmarking for Three-Independent-Gate Field Transistors," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 221-254, 2018.

  12. L. Amaru, P.-E. Gaillardon, S. Mitra, G. De Micheli, "Exploratory Logic Synthesis for Multiple Independent Gate FETs," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 255-272, 2018.

  13. X. Tang, P.-E. Gaillardon, I. O’Connor, G. De Micheli, "Ultrafine grain FPGAs with Polarity controllable Transistors," Functionality-Enhanced Devices: An alternative to Moore’s Law (Ed.: P.-E. Gaillardon), The Institution of Engineering and Technology, pp. 273-298, 2018.

  14. S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, R. Drechsler, "Logic Synthesis for Majority based In-Memory Computing," Memristors, Memristive Devices and Systems (Eds.: S. Vaidyanathan, C. Volos), Springer, pp. 425-448, 2017.

  15. P.-E. Gaillardon, J. Zhang, L. Amarú, G. De Micheli, "Multiple-Independent-Gate Nanowire Transistors: From Technology to Advanced SoC Design," Nano-CMOS and Post-CMOS Electronics: Vol. 1 Devices and Modeling (Eds.: S. P. Mohanty, A. Srivastava), The Institute of Engineering and Technology (IET), 2016.In press.

  16. X. Tang, S. Rahimian Omam, P. Meinerzhagen, P.-E. Gaillardon, G. De Micheli, "Low Power FPGAs based on Resistive Memories," Reconfigurable Logic: Architecture, Tools and Applications (Ed.: P.-E. Gaillardon), CRC press, pp. 399-432, 2015.

  17. D. Sacchetto, P.-E. Gaillardon, Y. Leblebici, G. De Micheli, "Memory Effects in Multi-terminal Solid State Devices and Their Applications," Memristor Networks (Eds.: A. Adamatzky, L. Chua), Springer, pp. 429-472, 2014.

  18. I. O'Connor, J. Liu, J. Kotb, N. Yakymets, R. Daviot, D. Navarro, P.-E. Gaillardon, F. Clermidy, M. Amadou, G. Nicolescu, "Emerging Technologies and Nanoscale Computing Fabrics," VLSI-SoC: Technologies for Systems Integration, IFIP Advances in Information and Communication Technology (Eds.: J. Becker, M. De Oliveira Johann, R. Reis), Springer, vol. 360, pp. 1-20, 2011.

Workshop and Conference Presentations

  1. M. Keyser, R. Gauchi, P. -E. Gaillardon, "An Energy-Efficient Three-Independent-Gate FET Cell Library for Low-Power Edge Computing," 2022 IFIP/IEEE 30th International Conference on Very Large Scale Integration (VLSI-SoC), 2022, Greece.

  2. K. Kelly, W. Xing, , T. Sayahi, T. Becnel, P.Goffin, A. Butterfield, M. Meyer, P.-E. Gaillardon, R. Whitaker "Using Networked Air Quality Sensors to Understand Neighborhood-Scale Differences in Particulate Matter Concentration During Pollution Episodes", ASIC, May 11-13, 2022, Pasadena, California.

  3. S. Temple, A. Snelgrove, W. Lau-Neto, P.-E. Gaillardon, “LSOracle: Modern Logic Synthesis for Complex Designs,” ERI Summit, October 19-21, 2021, Virtual.

  4. G. Gore, A. Pond, G. Brown, A. Alacchi, W. Tang, P.-E. Gaillardon, “OpenFPGA – An Enabler for 24-hour Prototyping for >100k-LUT Customizable FPGA Architectures,” ERI Summit, October 19-21, 2021, Virtual.

  5. P.-E. Gaillardon, P. Cadareanu, E. Giacomin, G. Gore, S. Temple, "Functionality-Enhanced Devices for Extending Moore’s Law," NSF Workshop on Micro/Nano Circuits and Systems design and Design Automation: Challenges and Opportunities, December 14-16, 2020, Virtual.

  6. G. Ammes, W. Lau Neto, P. Butzen, P.-E. Gaillardon, R. Ribas, "A Two-level Approximated Synthesis Method," 1st IEEE CASS/CEDA Seasonal School on Electronic Design Automation, December 7-11, 2020, Virtual. 2nd place best poster award.

  7. A. Alacchi, E. Giacomin, X. Tang, P.-E. Gaillardon, "Smart-Redundancy: a new SEU & SET Mitigation Method for FPGAs," 16th International School on the Effects of Radiation on Embedded Systems for Space Applications (SERESSA), December 1-4, 2020, Virtual.

  8. C. Mullen, S. Grineski, T. Collins, W. Xing, R. Whitaker, T. Sayahi, T. Becnel, P. Goffin, P-E. Gaillardon, M. Meyer, K. Kelly. "Distributive environmental injustice at Salt Lake County public schools for different PM2.5 air pollution scenarios," Poster, Global Change & Sustainability Center 2020 Environment & Sustainability Research Symposium, University of Utah, Salt Lake City, UT, February 2020.

  9. K. Kelly, W. Xing, P. Goffin, T. Sayahi, T. Becnel, P-E. Gaillardon, A.E. Butterfield, M. Meyer, R. Whitaker, "Understanding how pollution episodes affect community-level air quality with a distributed sensor network," AIChE Annual Meeting, Orlando, FL, November 10-15, 2019.

  10. J. Moore, W. Xing, M. Dailey, K. Le, T. Becnel, P. Goffin, M. Meyer, P-E Gaillardon, R.Whitaker, J. Wiese, A.E. Butterfield, K.E. Kelly, "Engaging middle and high school students in hypothesis generation using a citizen-scientist network of air quality sensors," AIChE Annual Meeting, Orlando, FL, November 10-15, 2019.

  11. T. Becnel and P.-E. Gaillardon, "A Low-Cost, Wearable Pollution Monitoring Device for Personal Exposure," 36th Annual Utah Conference on Safety and Industrial Hygiene, 10-11 October 2019, Salt Lake City, USA.

  12. M. Austin, W. Lau, S. Temple, X. Tang, P.-E. Gaillardon, "LSOracle: A Learning Based Oracle for Automatic Logic Optimization," ERI Summit, July 15-19, 2019, Detroit, MI, USA.

  13. T. Becnel, T. Sayahi, K. Kelly and P.-E. Gaillardon, "Online Calibration of a Low-Cost Pollution Monitoring Sensor Network," Work-in-Progress session, 54nd Design Automation Conference (DAC), 2-6 June 2019, Las Vegas, NV, USA.

  14. W. Lau Neto, X. Tang, M. Austin, L. Amaru, and P.-E. Gaillardon, "Improving Logic Optimization in Sequential circuits using Majority-inverter Graphs," Work-in-Progress session, 54nd Design Automation Conference (DAC), 2-6 June 2019, Las Vegas, NV, USA.

  15. B. Chauviere, A. Alacchi, E. Giacomin, X. Tang, P.-E. Gaillardon, "OpenFPGA: a Complete Open Source Framework for FPGA Prototyping," OSDA 2019 Workshop, 29 March 2019, Florence, Italy.

  16. J. Moore, W. Xing, Z. Wilhelm, M. Dailey, K. Le, T. Sayahi, T. Becnel, R. Whitaker, M. Meyer, J. Wiese, P.-E. Gaillardon, K. Kelly and A. Butterfield, "Engaging Middle and High School Student in Hypothesis Generation using a Citizen Scientist Network of Air Quality Sensors (Work in Progress)," 126th ASEE Annual Conference & Exposition, 15-19 June, 2019, Tampa, FL, USA.

  17. G. Resta, F. Catthoor, P.-E. Gaillardon and G. De Micheli, "Two-dimmensional materials for polarity-controllable FETs," contributed talk, Flatlands beyond Graphene, 3-7 September 2018, Leipzig, Germany.

  18. K.E. Kelly, P.-E. Gaillardon, R. Whitaker, M. Meyer, T. Butterfield, P. Goffin, T. Becnel, A. Biglari, D. Kaufman, T. Sayahi and W. Xing, "A layered framework for integrating low-cost sensor data and for engaging citizens to understand PM2.5 exposure," Poster, 10th International Aerosol Conference, 2-7 September 2018, St. Louis, MO, USA.

  19. E. Giacomin, T. Greenberg, S. Kvatinsky P.-E. Gaillardon, "A Robust Digital RRAM-based Convolutional Block for Low Energy Image Processing and Learning Applications," Work-in-Progress session, 53nd Design Automation Conference (DAC), 24-28 June 2018, San Francisco, CA, USA.

  20. G.Resta, Y. Balaji, T. Agarwal, I. P. Radu, D. Lin, F. Catthoor, P.-E. Gaillardon, G. De Micheli, "Polarity-controllable 2-dimensional transistors: experimental demonstration and scaling opportunities," 17th IEEE International Conference on Nanotechnology, 25-28 July 2017, Pittsburgh, PA, USA.

  21. M, Meyer, K. Kelly, P.-E. Gaillardon, Ross Whitaker, Neal Patwari, Tony Butterfield, "AQ and U: A Multidisciplinary Approach for Engaging and Informing Citizens About PM Exposure" Air Quality: Science for Solutions, 30 March 2017, Salt Lake City, UT, USA.

  22. P.-E. Gaillardon, "Design Opportunities of Resistive Back-End Memories: From Technology to Reconfigurable Logic," EPFL Logic Synthesis Forum, 27 March 2017, Lausanne, Switzerland.

  23. P.-E. Gaillardon, "Majority-based Synthesis for RRAM-based in-memory computing," Journées du club EEA, 4 November 2016, Marseille, France.

  24. M. Soeken, L. Amarú, P.-E. Gaillardon, G. De Micheli, "EPFL benchmark update at IWLS 2016," 26th International Workshop on Logic & Synthesis (IWLS), 10-11 June 2016, Austin, TX, USA.

  25. T.-H. Lin, T. Margossian, M. De Marchi, M. Thammasack, P.-E. Gaillardon, D. Baudouin, G. De Micheli, C. Copéret, "Low temperature synthesis of nickel silicide: from preparing colloidal nanoparticles to coating silicon," Swiss Chemical Society (SCS) Fall Meeting, 4 September 2015, Lausanne, Vaud, Switzerland.

  26. X. Tang, P.-E. Gaillardon, G. De Micheli, "RRAM-based FPGA Architecture: Non-Volatility and High-Performance," G-ReRAM International Workshop – Advances in ReRAM: Materials & Interfaces, 11-16 October 2015, Chania, Crete, Greece.

  27. P.-E. Gaillardon, L. Amarú, A. Siemon, E. Linn, R. Waser, A. Chattopadhyay, G. De Micheli, "Computing Secrets on a Resistive Memory Array," Work-in-Progress session, 52nd Design Automation Conference (DAC), 7-11 June 2015, San Francisco, CA, USA.

  28. O. Zografos, B. Sorée, A. Vaysset, S. Cosemans, L. Amarú, P.-E. Gaillardon, G. De Micheli, C. Adelmann, D. Wouters, R. Lauwereins, S. Sayan, P. Raghavan, D. Verkest, I. Radu, A. Thean, "Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS," Work-in-Progress session, 52nd Design Automation Conference (DAC), 7-11 June 2015, San Francisco, CA, USA.

  29. M. Thammasack, F. Messerschmitt, J. Rupp, P.-E. Gaillardon, G. De Micheli, "ReRAM technology developments for ultra-low power FPGA architectures," Nanoelectronics Days 2015 "GREEN-IT", 27-30 April 2015, Juelich, Germany.

  30. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "Fast Parametric Fault Modeling of Nanoscale Integrated Circuits," Designing with Uncertainty - Opportunities & Challenges Workshop, 13 March 2015, Grenoble, France.

  31. X. Tang, P.-E. Gaillardon, G. De Micheli, "High Performance Near-Vt RRAM-based FPGA: Opportunities for Low-Power Versatile Computing," HiPEAC Computing System Weeks (CSW), 8 October 2014, Athens, Greece.

  32. L. Amarú, A. Balatsoukas-Stimming, P.-E. Gaillardon, A. Burg, G. De Micheli, "Restructuring of Arithmetic Circuits with Biconditional Binary Decision Diagrams," University Booth, DATE conference 2014, Dresden, Germany.

  33. H. Ghasemzadeh, P.-E. Gaillardon, G. De Micheli, "Fast Process Variation Analysis in Emerging Nano-Scaled Technologies," Designing with Uncertainty - Opportunities & Challenges Workshop, 17-19 March 2014, York, United Kingdom.

  34. M. H. Ben Jamaa, M. De Marchi, P.-E. Gaillardon, I. O'Connor, F. Clermidy, G. De Micheli, "FPGA Design with Double-Gate Carbon Nanotube Transistors," Functionality-Enhanced Devices Workshop (FED), 25 March 2013, Lausanne, Switzerland.

  35. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Biconditional BDD: A Novel BDD Enabling Efficient Direct Mapping of DG Controllable Polarity FETs," Functionality-Enhanced Devices Workshop (FED), 25 March 2013, Lausanne, Switzerland.

  36. L. Amarú, P.-E. Gaillardon, G. De Micheli, "Logic Synthesis for Emerging Technologies," FETCH conference 2013, 7-9 January 2013, Leysin, Switzerland. BEST THESIS PRESENTATION AWARD

  37. D. Sacchetto, P.-E. Gaillardon, G. De Micheli, Y. Leblebici, "Advanced Technology Enablers for Next Design Paradigm," PhD Forum, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 07-10 October 2012, Santa Cruz, CA, USA.

  38. S. Bobba, P.-E. Gaillardon, V. Pavlidis, G. De Micheli, "Design Methodologies and CAD for 3D Monolithic Integration," MOTMOO12: DAC Workshop on More Than Moore Technologies, 03 June 2012, San Francisco, USAs.

  39. P.-E. Gaillardon, "From Simple Stacking to Real 3-D: a Design Opportunity", Chimtronique workshop: 3-D electronics architectures, 29 September 2011, Grenoble, France.

  40. K. Jabeur, P.-E. Gaillardon, I. O'Connor, M.H. Ben Jamaa, D. Navarro, F. Clermidy, N. Yakymets, "Logic cells and interconnect strategies for nanoscale reconfigurable computing fabrics," JNRDM 2011, 23-25 May 2011, Paris, France.

  41. P.-E. Gaillardon, M. H. Ben Jamaa, F. Clermidy, I. O'Connor, "Resistive-memory-based architectures for configurable logic circuits", EDAA-ACM SIGDA PhD Forum, DATE conference 2011, Grenoble, France.

  42. R. Daviot, P.-E. Gaillardon, K. Jabeur, D. Navarro, I. O'Connor, N. Yakymets, "Nanoreconfigurable logic clusters," Technologies émergentes et Green SoC-Sip, GDR SoC-SiP, 27-28 October 2011, Montpellier, France.

  43. M. H. Ben Jamaa, P.-E. Gaillardon, K. Mohanram, G. De Micheli, I. O'Connor, F. Clermidy, "Standard Cell and Fine-Grain Regular Fabric Design in Ambipolar Carbon Nanotube Technology", EDAA-ACM SIGDA PhD Forum, DATE conference 2010, Dresden, Germany.

  44. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Emerging devices based reconfigurable processing architectures," Connecting to the Nanoworld – Entretiens Jacques Cartier 2009, Lyon, France.

  45. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Architectures logiques reconfigurables à base de DG-CNTFETs: Intérêt de l’ambivalence," Chimtronique workshop, 14 October 2009, Saclay, France.

  46. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Using nanowires in reconfigurable processing architectures," Chimtronique workshop, 22 June 2009, Grenoble, France.

  47. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Reconfigurable processing architectures using emerging devices," GDR SoC SiP, 10-12 June 2009, Orsay, France.

  48. P.-E. Gaillardon, I. O'Connor, F. Clermidy, "Architectures numériques reconfigurables utilisant les propriétés des composants de l’électronique moléculaire," FETCH conference 2009, 12-14 January 2009, Chexbres, Switzerland.

  49. P.-E. Gaillardon, C. Béguet, V. Sénéclauze, "Positionnement absolu par trigonométrie laser," Journées pédagogiques du CNFM 2008, St Malo, France.