Reconfigurable Chiplets to Drive Reuse in Accelerator/System Designs - A Field-Programmable Accelerator Chiplet

Insights from the ACE Center show that chiplet-based systems provide a modular approach to high-performance heterogeneous architectures supporting diverse workloads. Fixed-function silicon maximizes efficiency and area utilization, but its rigidity limits integration flexibility and slows time to market. Re-configurable solutions such as Field-Programmable Gate Arrays (FPGAs) offer adaptability, though they typically fall short of specialized hardware in overall performance. Our contribution addresses the challenge of achieving both flexibility and efficiency through the design and silicon prototyping of domain-specific FPGA architectures. These FPGAs will interconnect ACE accelerator chiplets while also offloading tasks whose allocation may only be determined once the chiplet ensemble is composed. This work enables dynamically reconfigurable, modular hardware and aligns with the JUMP 2.0 goal to enable rapid, lower-cost design of specialized components and simplify integration of new compute elements, extending and reinvigorating ACE Task 002: Composable Distributed Acceleration. 

This research effort is funded by Semiconductor Research Corp.