OpenFPGA: An Automatic IP Generator for Customizable FPGA Architectures
Modern FPGA architectures are typically highly parameterized, leading to their routability and Performance, Power, Area (PPA) to fit diverse demands required by SoC implementations. However, modern FPGA fabric IPs typically require intensive manual efforts in development, such as hand optimized layouts. Very limited research and open-source efforts have been devoted to auto generation of customizable FPGA fabric IP blocks. We are developing an automatic IP generator for customizable FPGA architectures, as key element to kick-start a viable open source SoC ecosystem, which can significantly reduce the development and research (R&D) time required to embed custom FPGAs into SoCs. To enable this, our project include a SPICE generator, a Verilog generator and a bitstream generator, which is developed as add-ons to VPR tool suite.
To access the source codes, please visit: OpenFPGA Github.
Full documentation is available on: OpenFPGA Documentation.
Fig.: Proposed EDA flows based on Verilog Generator for accurate area, delay and power analysis.
This research effort is funded by DARPA, under the grant # FA8650-18-2-7855.